library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.alu_type.all;


entity TB_GLX is
end TB_GLX;

architecture TEST of TB_GLX is
component GLX_VLIW is
generic (	numBit	: integer := 32;
		Arch		: integer := 5;
		Ram_Size	: integer := 2;
		Rom_Size : integer := 72);
port (	clock		: in   std_logic;
		reset		: in   std_logic;
		vliw_en		: in   std_logic;
		result		: out std_logic_vector(numBit-1 downto 0);
		result_vliw	: out std_logic_vector(numBit-1 downto 0);
		ALUout		: out std_logic_vector(numBit-1 downto 0);
		ALUout_vliw	: out std_logic_vector(numBit-1 downto 0);
		NewPC		: out std_logic_vector(numBit-1 downto 0)
	);
end component;

signal CLK : std_logic := '0';
signal RST: std_logic;
signal vliw_en: std_logic;
signal result : std_logic_vector (31 downto 0);
signal result_vliw : std_logic_vector (31 downto 0);
signal ALUout : std_logic_vector (31 downto 0);
signal ALUout_vliw : std_logic_vector (31 downto 0);
signal newPC : std_logic_vector (31 downto 0);

begin

CLK_P: process (CLK)
	begin
		CLK <= not (CLK) after 50 ns;
	end process;

RST	<=	'1', '0' after 40 ns;
vliw_en <= '1', '0' after 1050 ns, '1' after 3050 ns;

CPU: GLX_VLIW port 
map(	clock		=> CLK,
		reset		=> RST,
		vliw_en		=> vliw_en,
		result		=> result,
		result_vliw	=> result_vliw,
		ALUout		=> ALUout,
		ALUout_vliw	=> ALUout_vliw,
		NewPC		=> newPC
	);

end TEST;
